Packaging carrier and manufacturing method thereof and chip package structure
US9374896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Jun 21, 2016 |
| Priority date | — |
| Expiry date | Nov 20, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49149
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A packaging carrier includes an interposer, a dielectric layer and a built-up structure. The interposer has a first surface and a second surface opposite to each other, and a plurality of first pads and second pads located on the first surface and the second surface, respectively. The dielectric layer has a third surface and a fourth surface opposite to each other. The interposer is embedded in the dielectric layer. The second surface of the interposer is not covered by the fourth surface of the dielectric layer, and has a height difference with the fourth surface. The built-up structure is disposed on the third surface of the dielectric layer and electrically connected to the first pads of the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.