Chip debug during power gating events
US9377506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Aug 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31705
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system, method, and tangible computer readable medium for chip debug is disclosed. For example, the system can include a plurality of functional blocks, a debug path, and a debug bus steering module. The debug path couples the plurality of functional blocks in a daisy chain configuration, where an end functional block from the plurality of functional blocks is at an end of the daisy chain configuration. The debug bus steering module is configured to pass one or more debug signals associated with a first functional block from the plurality of functional blocks along the debug path to the end functional block while a second functional block from the plurality of functional blocks performs one or more power gating cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.