Electronic device including a semiconductor memory unit that includes cell mats of a plurality of planes vertically stacked
US9377955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Sep 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane includes one or more cell mats. Each cell mat includes lower lines, upper lines crossing the lower lines, and variable resistance elements positioned in intersection regions of the lower lines and the upper lines, respectively. Lower contacts are coupled to the lower lines, respectively, and, in a plan view, overlap with a boundary region between half of the upper lines and the other half number of the upper lines. Upper contacts are coupled to the upper lines, respectively, and overlap with a boundary region between a half number of the lower lines and the other half number of the lower lines. One cell mat of an upper plane is vertically stacked over a lower plane to overlap with two adjacent cell mats of the lower plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.