Patent · US Active

Method and apparatus for performing integrated circuit layout verification

US9378325B2 · kind B2 · utility

0Cited by

16References

12Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Xavier Hours · Tournefeuille, FR
Shitiz Arora · Noida, IN
Robert S. Ruth · Austin, US

Key dates

Filing date	Feb 23, 2012
Grant date	Jun 28, 2016
Priority date	—
Expiry date	May 6, 2032

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02T10/82
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of performing layout verification for an integrated circuit (IC) layout is described. The method comprises receiving layout information for the IC layout, identifying at least one IC component within the IC layout, extracting localized layout information for the at least one IC component from the received layout information, defining the localized layout information for the at least one IC component within at least one component instance parameter therefor, and performing at least one layout verification check for the at least one component based at least partly on the at least one component instance parameter.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.