Memory controller and associated signal generating method
US9378800B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Apr 9, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Mar 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is directed to a memory controller and an associated signal generating method. By appropriately arranging a sequence according to which command signals are generated and expanding a latching interval of a part of address signals, not only the memory controller is enabled to control the DDR memory modules in a functional manner to further overcome issues of conventionally small latching intervals, but also system stability and access performance are reinforced as the memory access clock speed continue to increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.