Bitline regulator for high speed flash memory system
US9378834B2 · kind B2 · utility
5Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Sep 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.