Methods for forming interconnect layers having tight pitch interconnect structures

US9379010B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Christopher J. Jezewski · Portland, US
• Jasmeet S. Chawla · Hillsboro, US
• Kanwal Jit Singh · Hillsboro, US
• Alan M. Myers · Portland, US
• Elliot N. Tan · Portland, US
• Richard E. Schenker · Portland, US

Key dates

• Filing date: Jan 24, 2014
• Grant date: Jun 28, 2016
• Expiry date: Jan 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.