Grounding dummy gate in scaled layout design
US9379058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | May 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/966
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.