Assist gate structures for three-dimensional (3D) vertical gate array memory structure
US9379129B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2015 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Apr 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor strips which extend from a semiconductor pad. The layers are disposed so that the semiconductor strips in the plurality of layers form a plurality of stacks of semiconductor strips and a stack of semiconductor pads. Also, a plurality of select gate structures are disposed over stacks of semiconductor strips in the plurality of stacks between the semiconductor pad and memory cells on the semiconductor strips. In addition, different ones of the plurality of select gate structures couple the semiconductor strips in different ones of the stacks of semiconductor strips to the semiconductor pads in the plurality of layers. Further, an assist gate structure is disposed over the plurality of stacks between the select gate structures and the stack of semiconductor pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.