Integrated circuits and methods of forming integrated circuits
US9379208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.