Reduced variation MOSFET using a drain-extension-last process
US9379214B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Feb 9, 2015 |
| Grant date | Jun 28, 2016 |
| Priority date | — |
| Expiry date | Feb 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET structure and method of manufacture that minimize threshold variations associated with statistical uncertainties of implanted source and drain extensions. The source and drain extensions are fabricated very late in the process using a material added to etched recesses immediately adjacent to the transistor's channel. In various embodiments, the added material may be germanium grown by selective epitaxy, doped silicon grown by selective epitaxy, or metallic materials created by deposition or by deposition and reaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.