Method of diagnosable scan chain
US9383409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Apr 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for implementing a scan chain to test a semiconductor including obtaining an initial structure of the scan chain, determining, according to function modules of the semiconductor corresponding to scan registers on the scan chain, a first scan register pair with backward dependency, adjusting a structure of the scan chain such that the first scan register pair with backward dependency becomes a scan register pair with forward dependency, when a fan-in scan register in the scan register pair with backward dependency belongs to the key subset of the fan-out scan register in the first scan register pair with backward dependency, and determining a key subset of a fan-out scan register in the first scan register pair with backward dependency, wherein when all fan-in scan registers in the key subset reflect a same logic value, an output logic value of a function module connected to the fan-out scan register is fixed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.