Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers
US9383411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Three-dimensional processing systems are provided having one or more layers with circuitry that is dedicated to scanning and testing of other system layers, and which enables dynamic checkpointing, fast context switching and fast recovery of system state. For example, a semiconductor device includes a first chip and a second chip, which are physically conjoined to form a stacked structure. The first chip includes functional circuitry. The functional circuitry includes a plurality of scan cells such as scanable flip-flop and latches. The second chip includes scan testing circuitry, and a scan testing I/O (input/output) interface. The scan cells of the first chip are connected to the scan testing I/O interface of the second chip. The scan testing circuitry on the second chip operates to dynamically configure electrical connections between the scan cells on the first chip to form scan chains or scan rings for testing portions of the functional circuitry on the first chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.