Multi-core processor instruction throttling
US9383806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Mar 1, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.