Secondary CPU MMU initialization using page fault exception
US9383935B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jan 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system with multiple central processing units (CPUs), initialization of a memory management unit (MMU) for a secondary CPU is performed using an exception generated by the MMU. In general, this technique leverages the exception handling features of the secondary CPU to switch the CPU from executing secondary CPU initialization code with the MMU “off” to executing secondary CPU initialization code with the MMU “on.” Advantageously, in contrast to conventional techniques for MMU initialization, this exception-based technique does not require identity mapping of the secondary CPU initialization code to ensure proper execution of the secondary CPU initialization code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.