Inventor · Palo Alto, CA, US

Andrei Warkentin

71Patents
5h-index
35Co-inventors
68Inventor score

Filing activity: Mar 25, 2010 → Jan 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US10255090B2 Hypervisor context switching using a redirection exception vector in processors having more than two hierarchical privilege levels Physics 31 Active
US10162655B2 Hypervisor context switching using TLB tags in processors having more than two hierarchical privilege levels Physics 31 Active
US10002084B1 Memory management in virtualized computing systems having processors with more than two hierarchical privilege levels Physics 16 Active
US9465617B1 Implementing upcall from secure to non-secure mode by injecting exception into non-secure mode Physics 12 Active
US8775781B2 Intelligent boot device selection and recovery Physics 7 Active
US8612633B2 Virtual machine fast emulation assist Physics 4 Active
US10552172B2 Virtual appliance supporting multiple instruction set architectures Physics 3 Active
US9665378B2 Intelligent boot device selection and recovery Physics 3 Active
US9383935B1 Secondary CPU MMU initialization using page fault exception Physics 3 Active
US10282226B2 Optimizing host CPU usage based on virtual machine guest OS power and performance management Emerging Cross-Sectional Technologies 2 Active
US10642751B2 Hardware-assisted guest address space scanning in a virtualized computing system Physics 2 Active
US10620963B2 Providing fallback drivers for IO devices in a computing system Physics 2 Active
US9864708B2 Safely discovering secure monitors and hypervisor implementations in systems operable at multiple hierarchical privilege levels Physics 1 Active
US10185664B1 Method for switching address spaces via an intermediate address space Physics 1 Active
US11422840B2 Partitioning a hypervisor into virtual hypervisors Physics 1 Active
US10379870B2 Supporting soft reboot in multi-processor systems without hardware or firmware control of processor state Physics 1 Active
US11880301B2 Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space Physics 1 Active
US10853284B1 Supporting PCI-e message-signaled interrupts in computer system with shared peripheral interrupts Physics 1 Active
US11561894B2 Enabling efficient guest access to peripheral component interconnect express (PCIe) configuration space Physics 1 Active
US10261800B2 Intelligent boot device selection and recovery Physics 0 Active
US10795813B2 Implementing per-processor memory areas with non-preemptible operations using virtual aliases Physics 0 Active
US11693952B2 System and method for providing secure execution environments using virtualization technology Physics 0 Active
US10019275B2 Hypervisor context switching using a trampoline scheme in processors having more than two hierarchical privilege levels Physics 0 Active
US12277422B2 Device tree runtime mechanism Physics 0 Active
US9535772B2 Creating a communication channel between different privilege levels using wait-for-event instruction in systems operable at multiple levels hierarchical privilege levels Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.