Error code management in systems permitting partial writes
US9384091B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Aug 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1088
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory 10 stores a data block comprising a plurality of data values DV. An error code, such as an error correction code ECC, is associated with the memory and has a value dependent upon the plurality of data values which form the data block stored within the memory. If a partial write is performed on a data block, then the ECC information becomes invalid and is marked with an ECC_invalid flag. The intent is avoiding the need to read all data values to compute the ECC and thus save time and energy. The memory may be a cache line 28 within a level 1 cache memory 10. Memory scrub control circuitry 38 performs periodic memory scrub operations which trigger flushing of partially written cache lines back to main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.