Mechanisms for preventing leakage currents in memory cells
US9384815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.