Aligning calibration segments for increased availability of memory subsystem
US9384820B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for aligning calibration segments for increased availability of a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto via a number of independently operable channels (interfaces). The memory controller may convey on each of the channels at least one corresponding data strobe signal. The data strobe signal in each channel may be periodically calibrated. The memory controller may be configured to align the periodic calibrations in time so that they are performed concurrently instead of in a staggered manner. During the time the calibrations are performed on each channel, the memory may be unavailable for normal accesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.