Patent · US Active

SRAM array comprising multiple cell cores

US9384823B2 · kind B2 · utility

0Cited by

6References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Michael Kugel · Eppelheim, DE
Silke Penth · Holzgerlingen, DE
Raphael Polig · Dietikon, CH
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Sep 19, 2014
Grant date	Jul 5, 2016
Priority date	—
Expiry date	Sep 19, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/418
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An SRAM array having multiple cell cores to store and retrieve data. A cell core includes a plurality of SRAM cells, and at least two corresponding cell cores build a cell core row. A word decoder is configured to decode incoming address signals. The word decoder includes a cell core select unit configured to generate a cell core row select signal from a combination of a first part of the incoming address signals and a received clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.