Partial erase of nonvolatile memory blocks
US9384845B2 · kind B2 · utility
6Cited by
3References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 18, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Nov 18, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erasing blocks of a nonvolatile memory may include two erase steps. A first erase step brings the memory cells of a block to an intermediate state between their programmed states and an erased state. The block is then maintained with the memory cells in the intermediate state for a period of time. Subsequently, a second erase step on the block brings the memory cells from the intermediate state to the erased state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.