Semiconductor structure and method of forming the same
US9384984B2 · kind B2 · utility
5Cited by
21References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Sep 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided. The dielectric layer has a gate trench therein and a gate dielectric layer is formed on a bottom of the gate trench. A work function metal layer and a top barrier layer are sequentially formed in the gate trench. A treatment is performed to the top barrier layer so as to form a silicon-containing top barrier layer. A low-resistivity metal layer is formed in the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.