Dual-metal gate CMOS devices and method for manufacturing the same
US9384986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2012 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | May 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.