Patent · US Active

Dual-metal gate CMOS devices and method for manufacturing the same

US9384986B2 · kind B2 · utility

7Cited by
1References
10Claims
0Family size

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Key dates

Filing dateMay 17, 2012
Grant dateJul 5, 2016
Priority date
Expiry dateMay 17, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/8311
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.