Systems and methods involving data bus inversion memory circuitry, configuration and/or operation
US9385032B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Mar 17, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.