Replacement gate process
US9385044B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2013 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | May 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit containing metal replacement gates may be formed by forming a CMP stop layer over sacrificial gates, and forming a dielectric fill layer over the CMP stop layer. Dielectric material from the dielectric fill layer is removed from over the sacrificial gates using a CMP process which exposes the CMP stop layer over the sacrificial gates but does not expose the sacrificial gates. The CMP stop layer is removed from over the sacrificial gates using a plasma etch process. In one version, the plasma etch process may be selective to the CMP stop layer. In another version, the plasma etch process may be a non-selective etch process. After the sacrificial gates are exposed by the plasma etch process, the sacrificial gates are removed and the metal replacement gates are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.