STI region for small fin pitch in FinFET devices
US9385123B2 · kind B2 · utility
6Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2014 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | May 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to semiconductor devices, and particularly to fabricating a shallow trench isolation (STI) region in fin field effect transistors (FinFETs) having a small fin pitch. According to one embodiment, a method of using selective etching techniques to remove a single fin to form a fin trench and to form an isolation trench having a width approximately equal to a width of the single fin below the removed fin is disclosed. The fin trench and the isolation trench may be filled with isolation material to form an isolation region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.