Nanowire transistor with underlayer etch stops

US9385221B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Seiyon Kim · Portland, US
• Daniel B. Aubertine · North Plains, US
• Kelin J. Kuhn · Beaverton, US
• Anand S. Murthy · Beaverton, US

Key dates

• Filing date: Apr 16, 2015
• Grant date: Jul 5, 2016
• Expiry date: Apr 16, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures and/or drain the structures, when the material used in the fabrication of the source structures and/or the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures and/or the drain structures may be prevented.