Patent · US Active

Clock monitoring for sequential logic circuits

US9385700B2 · kind B2 · utility

0Cited by

1References

12Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Klemens Kordik · Linz, AT
Bernhard Gstoettenbauer · Felberleiten, AT
Klaus Buchner · Schaffhausen, CH
Thomas Sailer · Metzingen, DE

Key dates

Filing date	Sep 26, 2014
Grant date	Jul 5, 2016
Priority date	—
Expiry date	Sep 26, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K4/08
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A monitor circuit for monitoring a clock signal is described. In accordance with one example of the disclosure, the monitor circuit includes a pulse generator and a comparator circuit. The pulse generator is configured to generate a sequence of pulses synchronous to the clock signal, wherein each pulse has an edge with a monotonously rising or falling signal level. The comparator circuit receives the sequence of pulses and is configured to detect, for each clock cycle of the clock signal, whether or not the signal level of the sequence of pulses is outside a desired range at a specific time instant within the clock cycle of the clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.