Patent · US Active

Chip and method for manufacturing a chip

US9385726B2 · kind B2 · utility

2Cited by

2References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Kuenemund · Munich, DE
Bernhard Lippmann · Landshut, DE

Key dates

Filing date	Apr 17, 2014
Grant date	Jul 5, 2016
Priority date	—
Expiry date	Apr 17, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/85
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.