Combined floating point multiplier adder with intermediate rounding logic
US9389871B2 · kind B2 · utility
0Cited by
9References
30Claims
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Jan 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/45508
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.