Marc Lupon
18Patents
5h-index
32Co-inventors
62Inventor score
Filing activity: Dec 29, 2011 → May 3, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9978014B2 | Reconfigurable processing unit | Physics | 20 | Active |
| US9971540B2 | Storage device and method for performing convolution operations | Physics | 16 | Active |
| US9613001B2 | Processing device for performing convolution operations | Physics | 16 | Active |
| US9778909B2 | Double rounded combined floating-point multiply and add | Physics | 6 | Active |
| US9213523B2 | Double rounded combined floating-point multiply and add | Physics | 5 | Active |
| US9329848B2 | Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs | Emerging Cross-Sectional Technologies | 4 | Active |
| US9811341B2 | Managed instruction cache prefetching | Physics | 3 | Active |
| US9477441B2 | Double rounded combined floating-point multiply and add | Physics | 2 | Active |
| US10002108B2 | Processing device for performing convolution operations | Physics | 2 | Active |
| US10013326B2 | Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region | Physics | 1 | Active |
| US10997273B2 | Method and apparatus for distributed and cooperative computation in artificial neural networks | Emerging Cross-Sectional Technologies | 1 | Active |
| US9116719B2 | Partial commits in dynamic binary translation based systems | Physics | 1 | Active |
| US10402468B2 | Processing device for performing convolution operations | Physics | 0 | Active |
| US9389871B2 | Combined floating point multiplier adder with intermediate rounding logic | Physics | 0 | Active |
| US10061587B2 | Instruction and logic for bulk register reclamation | Physics | 0 | Active |
| US10157063B2 | Instruction and logic for optimization level aware branch prediction | Physics | 0 | Active |
| US12032653B2 | Method and apparatus for distributed and cooperative computation in artificial neural networks | Emerging Cross-Sectional Technologies | 0 | Active |
| US11281965B2 | Reconfigurable processing unit | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.