Three-dimensional processing system having independent calibration and statistical collection layer
US9389876B2 · kind B2 · utility
1Cited by
26References
20Claims
0Family size
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Key dates
| Filing date | Jan 13, 2014 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Nov 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein at least one chip layer has calibration control circuitry that is dedicated to calibrating/configuring one or more functional chip layers, and/or performance instrumentation control circuitry for testing and collecting performance data of one or more functional chip layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.