Method of minimizing the operating voltage of an SRAM cell
US9390786B2 · kind B2 · utility
5Cited by
8References
18Claims
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Key dates
| Filing date | Jul 30, 2015 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Jul 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM cell is formed of FDSOI-type NMOS and PMOS transistors. A doped well extends under the NMOS and PMOS transistors and is separated therefrom by an insulating layer. A bias voltage is applied to the doped well. The applied bias voltage is adjusted according to a state of the memory cell. For example, a temperature of the memory cell is sensed and the bias voltage adjusted as a function of the sensed temperature. The adjustment in the bias voltage is configured so that threshold voltages of the NMOS and PMOS transistors are substantially equal to n and p target threshold voltages, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.