Semiconductor memory and semiconductor memory control method
US9390800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2013 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Aug 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory includes memory cells, word lines connected to gate of memory cells arranged in a row direction, a control circuit which controls the operation of the memory cells. During k-level data writing to a selected cell, the control circuit applies the corrected unselect voltage in accordance with the result of the reading of data from the unselected cell connected to the adjacent word line to the adjacent word line and applies a read voltage to the selected word line to read (k−1)-level data from the selected cell, and the control circuit writes data to the selected cell in accordance with the read (k−1)-level and the k-level data to be written.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.