Process for forming wide and narrow conductive lines
US9390922B1 · kind B1 · utility
1Cited by
24References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2015 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Feb 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Sidewall spacers formed on sides of mandrels are separated by first gaps in a first region and separated by wider second gaps in a second region. The second gaps are filled while a capping layer caps the first gaps. The capping layer is etched thereby exposing mandrels in the first region, which are removed. An underlying layer is patterned using the sidewall spacers separated by first gaps to form word lines in the first region and using sidewall spacers with filled second gaps to form select lines in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.