Semiconductor package
US9391048B2 · kind B2 · utility
12Cited by
10References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 7, 2014 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Jun 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package, comprising: a substrate; a first semiconductor chip; and at least one second semiconductor chip. The first semiconductor chip and the at least one second semiconductor chip are stacked on the substrate; the first semiconductor chip is electrically connected with the substrate; and an electrical connection of each second semiconductor chip is formed through a secondary input/output buffer of the first semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.