Stacked planar double-gate lamellar field-effect transistor

US9391163B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Josephine B. Chang · Mahopac, US
• Michael A. Guillorn · Locke, US
• Gen P. Lauer · Mahopac, US
• Isaac Lauer · Yorktown Heights, US
• Jeffrey W. Sleight · Ridgefield, US

Key dates

• Filing date: Oct 3, 2014
• Grant date: Jul 12, 2016
• Expiry date: Oct 3, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.