Method of joining a chip on a substrate
US9393633B2 · kind B2 · utility
0Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2009 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.