Cache allocation scheme optimized for browsing applications
US9396122B2 · kind B2 · utility
2Cited by
24References
20Claims
0Family size
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Key dates
| Filing date | Apr 19, 2013 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Oct 10, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.