System translation look-aside buffer integrated in an interconnect
US9396130B2 · kind B2 · utility
1Cited by
26References
23Claims
0Family size
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Key dates
| Filing date | Aug 16, 2013 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Aug 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.