Semiconductor memory device including a control circuit and at least two memory cell arrays
US9396775B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Sep 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.