Stacked memory device and system
US9396777B1 · kind B1 · utility
4Cited by
0References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 28, 2015 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | May 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.