Conformity control for metal gate stack
US9396953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Mar 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess. The metal layer is over the gate dielectric layer. The formation of the metal layer includes placing the wafer against a target, applying a DC power to the target, and applying an RF power to the target, wherein the DC power and the RF power are applied simultaneously. A remaining portion of the recess is then filled with metallic materials, wherein the metallic materials are overlying the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.