Methods and apparatus for wafer level packaging
US9396973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2015 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Mar 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.