Co-integration of different fin pitches for logic and analog devices

US9397006B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Injo Ok · Lockport, US
• Balasubramanian Pranatharthiharan · Watervliet, US
• Soon-Cheon Seo · White Plains, US
• Charan V. Surisetty · Clifton Park, US

Key dates

• Filing date: Dec 4, 2015
• Grant date: Jul 19, 2016
• Expiry date: Dec 4, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

A method includes forming a first set of fins on a substrate; forming a second set of fins on the substrate; forming a gate stack over the fins and substrate; depositing a spacer layer around each fin in the first set of fins and in the second set of fins and the substrate; etching horizontal and vertical surfaces covered by the spacer layer to form spacers around the first set of fins and the second set of fins; etching horizontal and vertical surfaces of the spacer to pull down the spacer around the second set of fins; growing an epitaxy layer around the first set of fins and the second set of fins and growing epitaxy on the first set of fins and on the second set of fins; merging the epitaxy on the first set of fins; and merging the epitaxy on the second set of fins.