Patent · US Active

Package in package (PiP) electronic device and manufacturing method thereof

US9397068B2 · kind B2 · utility

1Cited by
2References
5Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 4, 2012
Grant dateJul 19, 2016
Priority date
Expiry dateDec 4, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/3011
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.