Multiple die lead frame packaging
US9397082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2016 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Jan 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48247
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
First and second semiconductor die are mounted to first and second die pads of a lead frame disposed in a lead frame sheet. With a plurality of wire bonds, each post of a plurality of posts of the lead frame is connected to the first and second semiconductor die. Each post extends inward from opposite sides of the lead frame between the first and second die pads and is connected with a respective one of a plurality of leads of the lead frame. The first and second semiconductor die, the plurality of posts of the lead frame, and the plurality of wire bonds are encapsulated in a package. The lead frame sheet is sheared to define each lead of the plurality of leads. The plurality of posts includes first and second sets of posts extending inward from first and second opposite sides of the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.