Stacked common gate finFET devices for area optimization

US9397101B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Harikrishna Chintarlapalli Reddy · Bengaluru, IN
• Jay M. Shah · Bengaluru, IN
• Ananth Haliyur Gopalakrishna · Bengaluru, IN

Key dates

• Filing date: Aug 12, 2014
• Grant date: Jul 19, 2016
• Expiry date: Mar 26, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain.