Multi-gate device structure including a fin-embedded isolation region and methods thereof
US9397157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Aug 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for implementation of high voltage devices within multi-gate device structures includes a substrate having a fin extending therefrom and a fin-embedded isolation region. In some examples, the fin-embedded isolation region includes an STI region. In some embodiments, the fin-embedded isolation separates a first portion of the fin from a second portion of the fin. Also, in some examples, the first portion of the fin includes a channel region. In various embodiments, a source region is formed in the first portion of the fin, a drain region is formed in the second portion of the fin, and an active gate is formed over the channel region. In some examples, the active gate is disposed adjacent to the source region. In addition, a plurality of dummy gates may be formed over the fin, to provide a uniform growth environment and growth profile for source and drain region formation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.