Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices
US9397219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2015 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.